1. Technical Field
The present disclosure relates generally to information processing systems and, more specifically, to register renaming for all bits or specified bits of a logical register with multiple accessible bit fields.
2. Background Art
Compiled or assembled software instructions reference certain logical registers defined in the instruction set for a target processor. Register renaming is the remapping (renaming) of logical registers to physical registers. Register renaming is used to increase the number of instructions that a superscalar processor can issue in parallel. Superscalar processors attempt to exploit instruction level parallelism by issuing multiple instructions in parallel, thus improving performance. Register renaming improves performance of code not specifically compiled for a superscalar processor because such code tends to use logical registers in ways that reduce the amount of parallelism available.
The instruction set for a processor typically includes a limited number of available logical registers (the number of logical registers being less than the number of physical registers available in the processor). As a result, the same logical register is often used in compiled code to represent many different variables, although only one variable is represented by a logical register at any given time. Because the same register is used to represent different variables, the values of these variables are independent. Renaming each of these independent uses of a logical register to different physical registers allows multiple variables to exist concurrently in the physical registers. This renaming prevents dependence-induced delays by removing WAR (write-after-read) and WAW (write-after-write) dependencies and by allowing multiple independent instructions that utilize the same logical register to be issued concurrently.
Some processors, such as the Itanium® and Itanium II® microprocessors available from Intel Corporation in Santa Clara, Calif., include one or more registers for which partial-bit access is permitted. For example, the Explicitly Parallel Instruction Computing (“EPIC”) architecture utilized by Itanium® and Itanium II® microprocessors features a predicate register (sometimes referred to herein as “PR”) that contains 64 separate predicate bit fields to support predication.
Predication is a method of converting control flow dependencies to data dependencies. In general, a predicated instruction is associated with a single-bit “predicate” that controls the execution of the instruction. The processor commits the semantic results of a predicated instruction only if that instruction's predicate bit is true.
Each field of the predicate register may hold a predicate value for a specific instruction. The value in a bit of the predicate register therefore indicates whether or not conditional execution of the associated instruction should occur.
For at least one embodiment, the bits of the PR may be accessed singly or in pairs. In addition, the upper 48 bits of the PR may be accessed by a single instruction. Also, all bits of the PR may be accessed by a single instruction. A single bulk renaming of the PR register to a physical register may lead to unnecessary stalls between two instructions that access different bits or bit-pairs within the PR.